The present invention relates to the field of data transmission, and more particularly, to synchronizing to asynchronous data transmissions. One embodiment is related to synchronizing a sampling clock to an asynchronous serial digital data stream.
Asynchronous serial digital transmission is a common form for transferring information in the telecommunication industry. A device that is receiving an asynchronous stream of data must sample the data stream at times when the data is stable in order to guarantee accurate reception of the data stream. A typical receiving device may use an internal sampling clock to sample the serial data stream. However, an asynchronous serial data stream is, by its nature, asynchronous to the internal sampling clock. Therefore, if the data stream is simply sampled on edges of the internal clock, the receiving device may not be assured that each time data is sampled, correct data will be received. This is because even though the frequency of the internal clock may be the same as the data stream transmission rate, the phase between the sampling clock and the data stream may drift so that clock edges of the sampling clock occur during times when data on the data stream is unstable. Therefore, it would be desirable for a device that is receiving an asynchronous stream of data to somehow synchronize its internal sampling clock to the incoming asynchronous data in such a way as to guarantee that the serial data is stable when it is sampled. Moreover, it is desirable that the synchronization process be done in a way such that data is not lost.
If the incoming serial data stream is well defined in terms of bit rate, transmission time, and threshold values, and this information is known to the receiving device, then the synchronization problem is simplified. However, the problems of synchronization are compounded if no assumptions can be made about the incoming serial data stream. For example, if a receiving device must be capable of receiving asynchronous data streams at different transmission rates, then the synchronization logic must be able to handle changes in the transmission rate. Traditional synchronization solutions such as a phase locked loops are ineffective for synchronizing to an asynchronous serial digital data stream. This is because a phase locked loop must synchronize to a periodic reference. However, an asynchronous digital data stream may not be periodic. For example, if the bit stream 10011 is transmitted, there is no transition edge in the data stream for two consecutive bit periods. The problem is exacerbated when long strings of zeros or ones are transmitted. Therefore, a traditional phase locked loop would not be able to maintain synchronization. Thus, it is desirable to have a receiving device for receiving an asynchronous data signal that samples the data signal at times when each bit is stable without missing any bits. To accomplish this, it would be desirable to be able to synchronize an internal sampling clock to an asynchronous data signal.
Furthermore, conventional phase locked loops may require several clock cycles to synchronize. Thus, data may be lost for the periods before synchronization is completed. Thus, it is desirable to shorten the amount of time required to synchronize. Preferably, synchronization (or phase locking) would occur immediately.
If the asynchronous data stream is a serial digital data stream, once the data is received it may be necessary to convert the data from a serial format to a parallel format. Also, if data is to be transmitted from the same device it may be necessary to convert parallel data into serial data for transmission. Similarly, if parallel data is received as the transmitted data, in some applications it may be desirable to convert to serial data and vice versa. Typically, a shift register is used to convert data from a serial format to a parallel format or from a parallel format to a serial format. Typically the shift register is of a fixed length and a counter is used to indicate when all the bits in the shift register have been shifted in or out. However, if the length of data words to be converted is not a fixed value then a conventional fixed length shift register and counter may not be used. Likewise, if the word length of the data must be dynamically altered, a fixed length shift register and counter are inappropriate. Furthermore, as the length of the word to be converted increases, so must the complexity of the counter used to track the status of the conversion. In high speed applications involving long data words the counter size may be prohibitive as to the speed at which the parallel-to-serial or serial-to-parallel converter may operate.
It would thus be desirable to have a general purpose serial-to-parallel or parallel-to-serial converter that provides the capability to convert the data format for variable word sizes. Also, it would be desirable for the data converter to scale with changes in the word size with negligible impact on performance.
Devices for receiving and/or transmitting serial data streams may often be implemented as custom circuit designs. However, when it becomes necessary to upgrade the device to a new process or new technology or to provide for faster transmission rates or different data formats, such custom designs may not scale well in terms of size and performance. A custom logic design that works for one type of semiconductor component, such as a gate array employing a certain process and operating frequency, may not operate if the process or operating frequency is changed. It would be desirable to have a design for sampling asynchronous data transmissions and converting the data stream from serial-to-parallel or parallel-to-serial formats where the design is easily scaled to different device processes operating speeds and architectures.
Synchronization logic for synchronizing a sample clock to an asynchronous data sample is described. One embodiment of the synchronization logic may include a counter for measuring the time between a transition edge of the data on the asynchronous data signal and a sample edge of the sample clock. If the time between these two events is less than a dead-band value or if these two events occur concurrently, then a warning signal may be generated to indicate that the sample clock edge occurred too close to the data transition to ensure that the data sample will be valid. The warning signal may be used to readjust the phase of the sample clock so that sample transitions will occur during times when the data is stable on the asynchronous data signal.
Sample clock synchronization logic for sampling an asynchronous data signal may include a bit-rate counter which creates a terminal count clock signal that approximately matches the data rate frequency of the asynchronous data signal. A phase delay counter may be used to generate the sample clock signal at a phase delay from the terminal count clock signal provided by the bit-rate counter. An edge detector may be provided to determine when a transition occurs on the asynchronous data signal. The edge detector may provide an edge signal to glue logic to indicate when such a data transition has occurred. The glue logic may then cause the bit-rate counter and phase delay counter to be restarted so that the phase of the sample clock is readjusted. This will cause the sample clock edge to occur at approximately the phase delay count value from the edge of the data transition on the asynchronous data signal, thus assuring correct sampling.
The bit-rate counter may be programmable such that a bit-rate value is loaded into the bit-rate counter to select the frequency at which the terminal count clock signal will be generated. Also, a subtracter may be employed to subtract the count value of the bit-rate counter from the programmed bit-rate value. The difference from the subtracter may be compared to a dead-band value to determine if the sample clock transition will occur too close to an edge on the asynchronous data signal. If it is determined that the sample clock edge will occur too close to a data transition, then a warning signal may be generated.
An apparatus for receiving an asynchronous data signal is contemplated. The apparatus may include a clock signal generator configured to generate a clock signal having a frequency approximately equal to the bit rate of the asynchronous data signal. Also, circuitry may be included for receiving the asynchronous data signal at times determined by a transition of the clock signal. An edge detector may be configured to detect a transition of the asynchronous data signal and a dead-band detector may be coupled to the clock signal generator and to the edge detector for detecting when the transition of the clock signal occurs within a predetermined amount of time of the transition of the asynchronous data signal. The phase of the clock signal may be adjusted if the transition of the clock signal occurs within the predetermined amount of time of the transition of the asynchronous data signal. The dead-band detector may be further configured to assert a bad sample signal or and edge-too-close signal when the transition of the clock signal occurs within the predetermined amount of time of the transition of the asynchronous data signal. The bad sample signal may allow the apparatus to take corrective action such as resembling the asynchronous data signal or ignoring a potential bad sample. The edge detector may be configured to assert an edge signal upon detection of the transition of the asynchronous data signal, and the phase of the clock signal may be adjusted in response to the edge signal. The edge detector may be configured to assert the bad sample signal when the transition of the clock signal occurs within the predetermined amount of time before assertion of the edge signal or concurrently therewith.
The clock signal generator may comprise a bit-rate counter configured to generate a count signal corresponding to the bit rate of the asynchronous data signal. The clock signal generator may also include a phase counter adapted to generate the clock signal at a phase delay from the count signal. The bit-rate counter and phase counter may be reset in response to a transition of the asynchronous data signal. Also, the phase counter and bit rate counter may be programmable such that a phase value may be loaded into the phase counter to select the phase delay and a bit-rate value may be loaded into the bit-rate counter select the frequency of the count signal to match the frequency of the asynchronous data signal.
The dead-band detector may comprise a subtracter configured to subtract a count value from the bit-rate value and output the difference. The count value may be the count of the bit-rate counter. The dead-band detector may also include a comparitor to compare the difference from the subtracter to a dead-band value. The difference indicates how close the transition of the clock signal occurs to the transition of the asynchronous data signal. The dead-band value may represent the predetermined amount of time. The circuitry configured to receive the asynchronous data signal may include a serial-to-parallel converter. The serial-to-parallel converter may include one or more shift registers which may be clocked by the clock signal.
A method for synchronizing a clock signal to an asynchronous data signal is contemplated. The method may include generating a clock signal where the frequency of the clock signal is selected to be approximately equal to the bit rate of the asynchronous data signal. The method may also include detecting a transition of the asynchronous data signal and detecting if a sample transition of the clock signal occurs within a predetermined amount of time of the transition of the asynchronous data signal. An indication of such an event may be generated. The method also may include adjusting the phase of the clock signal so that the next sample transition of the clock signal will occur a phase delay from the transition of the asynchronous data signal. Generating a clock signal may include counting for a time period corresponding to the bit rate of the asynchronous data signal and generating a terminal count signal when the time period is reached. Generating a clock signal may also include counting for a phase delay from the terminal count signal and asserting the clock signal when the phase delay is reached. Adjusting the phase of the clock signal may include restarting the counting for a time period and counting for the phase delay in response to detecting a transition of the asynchronous data signal. Generating a clock signal may further include loading a first programmable counter with a bit-rate count value corresponding to the bit rate of the asynchronous data signal and loading a second programmable counter with a phase delay counting value corresponding to the phase delay. Detecting if a sample transition of the clock signal occurs within a predetermined time of the transition of the asynchronous data signal may include subtracting a count value from the bit-rate count value and outputting the difference. The bit-rate count value may be provided by the counting for a time period as described above. The detecting may also include comparing the difference from the subtracting to a dead-band value. The difference indicates how close the sample transition of the clock signal occurs to the transition of the asynchronous data signal and the dead-band value represents the predetermined amount of time described above. The frequency of the clock signal may be changed in response to a change, or anticipated change, in the bit rate of the asynchronous data signal. This may be performed by loading a new bit-rate count value into a bit-rate counter.
The clock synchronization techniques described above may be employed in conjunction with a serial-to-parallel data converter. A serial-to-parallel data converter may include a first shift register configured to shift in a data word (from the asynchronous data signal) and output the data word in parallel. The serial-to-parallel converter may also include a second shift register configured to track when the data word has been completely shifted into the first shift register and to cause the data word to be outputted in parallel form from the first shift register. The second shift register may be programmable so that it may be loaded with a value corresponding to the number of bits in the data word to be converted. This value may be shifted in the second shift register each time a bit of the data word is shifted into the first shift register so that an output indication is shifted out of the second shift register as the last bit of the data word is shifted into the first shift register. The first shift register may be configured to convert data words of varying bit lengths from serial-to-parallel format. The bit size of the first shift register may be equal to the maximum bit length to be converted. The second shift register may be adapted to track different bit lengths by receiving different shift status words corresponding to the bit length of the data word to be converted. Thus, by changing the status word loaded into the second shift register, the bit length to be converted may be changed dynamically.
A parallel-to-serial converter is also contemplated. The parallel-to-serial converter may include a first shift register configured to receive a data word in parallel and shift out the data word serially. A second shift register may also be included, configured to track when the data word has been completely shifted out of the first shift register and to cause a new data word to be loaded in parallel into the first shift register. The second shift register may be loaded with a value corresponding to the number of bits in the data word. This value may be shifted in the second shift register each time a bit of the data word is shifted out of the first shift register so that a load indication is shifted out of the second shift register when the last bit of the data word is shifted out of the first shift register. This load indication may be used to indicate when a new parallel word and shift status value may be loaded into the first and second shift registers respectively. The first shift register may be configured to convert data words of various bit lengths from parallel-to-serial format. The bit size of the first shift register may be equal to the maximum bit length to be converted. The second shift register may be adapted to track different bit length by receiving a shift status word corresponding to the bit length of the data word to be converted. Thus, by loading a different shift status word or value into the second shift register, the bit length to be converted may be changed dynamically.
A data converter is also contemplated including a first shift register configured to perform a data conversion by shifting in a data word serially and outputting the data word in parallel, or receiving the data word in parallel and outputting serially, as determined by a direction signal. A second shift register may be configured to track when the data conversion has been completed and to cause the data conversion to be performed on the next data word. A second shift register may be loaded with a value corresponding to the number of bits in the data word to be converted. This value is shifted in the second shift register each time a bit of the data word is shifted into or out of the first shift register so that a conversion complete indication is shifted out of the second shift register when the last bit of the data word is converted in the first shift register. The first shift register may be configured to convert data words of varying bit lengths and the bit size of the first shift register may be equal to the maximum bit length to be converted. The second shift register may be adapted to track different bit lengths by receiving a shift status word corresponding to the bit length of the data word to be converted. Thus, the bit length to be converted may be changed dynamically by changing the value of the shift status word.
Also contemplated is a method for tracking the conversion of a data word from parallel-to-serial or from serial-to-parallel format. The method includes shifting a data word in to or out of a first shift register according to a conversion type indication. The method also includes shifting a value in the second shift register each time data in the first shift register is shifted. The method includes outputting a conversion complete indication from the second shift register when the conversion is complete. This conversion complete indication may be used to indicate when conversion of a new data word may begin. The method may also include loading the second shift register with a value corresponding to the number of bits in the data word to be converted. The first shift register may be configured to convert data words of varying bit lengths where the bit size of the first shift register is equal to the maximum bit length to be converted. The method may also include dynamically changing the data word bit length to be converted by changing the value loaded in the second shift register between conversions.
The logic for synchronizing a sample clock to an asynchronous data stream and the data converters described above may be used in conjunction in a device for receiving and/or transmitting serial data. For example, the sample clock synchronized to the asynchronous data stream may be used to indicate when the asynchronous data should be shifted in to the serial-to-parallel converter as described above to insure that valid data samples are shifted into the shift register. Also, the parallel-to-serial converter described may be employed to convert parallel data received from, for example, a computer interface to serial data to be transmitted as part of the asynchronous data transmission stream.